The present disclosure generally relates to semiconductor devices, and particularly to complementary metal-oxide-semiconductor (CMOS) field effect transistors including epitaxial source and drain extension regions, and methods of manufacturing the same.
With scaling of semiconductor devices, the distribution of electrically active dopants in source and drain extension regions of a metal-oxide-semiconductor field effect transistor (MOSFET) is statistically determined. Further, the extent of the source and drain regions becomes more difficult to control with the reduction of lateral dimensions for the source and drain regions. Thus, the resistance of the source and drain regions is subjected to greater statistical variation, i.e., control of the resistance of source and drain extension regions becomes more difficult with the scaling.
However, the performance of a MOSFET is often critically dependent on the resistance of the source and drain extension regions. Specifically, high source or drain resistance in a MOSFET results in degradation in the on-current and the switching speed of the MOSFET. Thus, the resistance of the source and drain extension regions needs to be kept low in order to provide a high performance MOSFET.
Further, ion scattering effect that accompanies conventional ion implantation process employed to doped source and drain extension regions causes short channel effect (SCE) performance degradation in high performance MOSFETs. The stochastic nature of the path of the implanted electrical dopants (which are either p-type dopants or n-type dopants) causes the dopant concentration profile around interfaces between a body region of a MOSFET and source and drain extension regions of the MOSFET to vary gradually due to significant interdiffusion of electrical dopants between the body region and the source and drain extension regions, thereby exacerbating the short channel effect.